Main Processor (Versal) Development

This chapter describes how to develop the Main Processor implemented with the Versal device.

The provided development environment is configured with the standard features enabled for the SC-OBC Module V1 as implemented on the onboard hardware. Users can extend this environment by adding the functions required for their mission, enabling them to implement the capabilities needed for their spacecraft.

Directory Structure of the Development Environment

Before building, the Versal development environment has the following structure:

 versa               # Main Processor (Versal) FPGA project
  ├─ rtl/            # RTL sources
  ├─ ip/             # IP core configuration files
  ├─ constraints/    # Design constraint files
  ├─ script/         # Build scripts
  └─ work/           # **Generated after the first build**
        └ implement   # Work directory for FPGA implementation

When running make implement inside the versal directory, a work/implement/project directory is created. Vivado generates and expands the full set of project files inside this project directory.