Interface Specifications

CON1 (Carrier Board Interface)

The SC-OBC Module V1 connects to the Carrier Board via a 400-pin Board-to-Board connector manufactured by Samtec. All input and output signals of the SC-OBC Module V1, including debug signals, are exchanged through this Board-to-Board connector.

Interface Signals
Figure 1. Interface Signals

The connector implemented on the OBC module side is SEAF-40-05.0-S-10-1-A-K-TR. Therefore, the Carrier Board must be equipped with a mating SEAM-40-xxxx-S-10 series connector (where xxxx ranges from 02.0 to 11.0 depending on the required stack height).

CON1 Pin Layout

Table 1. Board to Board Connector Pin Layout (Columns A–D)
Pin
Number		 A B C D

1

GTYP_REFCLKP0_103

GTYP_REFCLKN0_103

GND

GND

2

GND

GND

GTYP_TXP0_103

GTYP_TXN0_103

3

GTYP_RXP0_103

GTYP_RXN0_103

GND

GND

4

GND

GND

GTYP_TXP1_103

GTYP_TXN1_103

5

GTYP_RXP1_103

GTYP_RXN1_103

GND

GND

6

GND

GND

GTYP_TXP2_103

GTYP_TXN2_103

7

GTYP_RXP2_103

GTYP_RXN2_103

GND

GND

8

GND

GND

GTYP_TXP3_103

GTYP_TXN3_103

9

GTYP_RXP3_103

GTYP_RXN3_103

GND

GND

10

GND

GND

GTYP_REFCLKP1_103

GTYP_REFCLKN1_103

11

GTYP_REFCLKP0_104

GTYP_REFCLKN0_104

GND

GND

12

GND

GND

GTYP_TXP0_104

GTYP_TXN0_104

13

GTYP_RXP0_104

GTYP_RXN0_104

GND

GND

14

GND

GND

GTYP_TXP1_104

GTYP_TXN1_104

15

GTYP_RXP1_104

GTYP_RXN1_104

GND

GND

16

GND

GND

GTYP_TXP2_104

GTYP_TXN2_104

17

GTYP_RXP2_104

GTYP_RXN2_104

GND

GND

18

GND

GND

GTYP_TXP3_104

GTYP_TXN3_104

19

GTYP_RXP3_104

GTYP_RXN3_104

GND

GND

20

GND

GND

GTYP_REFCLKP1_104

GTYP_REFCLKN1_104

21

VCCO_302_IN

VCCO_302_IN

GND

GND

22

IO_L0P_302

IO_L0N_302

GND

IO_L5P_HDGC_302

23

GND

IO_L3P_302

IO_L3N_302

GND

24

IO_L1P_302

IO_L1N_302

GND

IO_L6P_HDGC_302

25

GND

IO_L4P_302

IO_L4N_302

GND

26

IO_L2P_302

IO_L2N_302

GND

IO_L7P_302

27

GND

IO_L6P_GC_XCC_N2P0_703

IO_L6N_GC_XCC_N2P1_703

GND

28

IO_L0P_XCC_N0P0_703

IO_L0N_XCC_N0P1_703

GND

IO_L12P_GC_XCC_N4P0_703

29

GND

IO_L7P_N2P2_703

IO_L7N_N2P3_703

GND

30

IO_L1P_N0P2_703

IO_L1N_N0P3_703

GND

IO_L13P_N4P2_703

31

GND

IO_L8P_N2P4_703

IO_L8N_N2P5_703

GND

32

IO_L2P_N0P4_703

IO_L2N_N0P5_703

GND

IO_L14P_N4P4_703

33

GND

IO_L9P_GC_XCC_N3P0_703

IO_L9N_GC_XCC_N3P1_703

GND

34

IO_L3P_XCC_N1P0_703

IO_L3N_XCC_N1P1_703

GND

IO_L15P_XCC_N5P0_703

35

GND

IO_L10P_N3P2_703

IO_L10N_N3P3_703

GND

36

IO_L4P_N1P2_703

IO_L4N_N1P3_703

GND

IO_L16P_N5P2_703

37

GND

IO_L11P_N3P4_703

IO_L11N_N3P5_703

GND

38

IO_L5P_N1P4_703

IO_L5N_N1P5_703

GND

IO_L17P_N5P4_703

39

GND

IO_L24P_GC_XCC_N8P0_703

IO_L24N_GC_XCC_N8P1_703

GND

40

VCCO_703_IN

VCCO_703_IN

VCCO_302_703_PWREN

CCO_302_703_PWREN
Table 2. Board to Board Connector Pin Layout (Columns E–H)
Pin
Number		 E F G H

1

VCC_BATT_IN

GND

VIN_5V0

VIN_5V0

2

GND

GND

VIN_5V0

VIN_5V0

3

VCC_BATT_IN

GND

VIN_5V0

VIN_5V0

4

GND

GND

GND

GND

5

M2GL_MSIO222PB5

M2GL_MSIO222NB5

M2GL_MSIO208PB5

M2GL_MSIO208NB5

6

GND

M2GL_MSIO226PB5

M2GL_MSIO209PB5

M2GL_MSIO209NB5

7

M2GL_MSIO228PB5

M2GL_MSIO226NB5

M2GL_MSIO212PB5

M2GL_MSIO212NB5

8

GND

M2GL_MSIO228NB5

M2GL_MSIO213PB5

M2GL_MSIO213NB5

9

M2GL_MSIO230PB5

M2GL_MSIO230NB5

M2GL_MSIO216PB5

M2GL_MSIO216NB5

10

GND

RSVD

M2GL_MSIO221PB5

M2GL_MSIO221NB5

11

M2GL_MSIO156PB8

M2GL_MSIO156NB8

GND

GND

12

GND

M2GL_MSIO157PB8

M2GL_MSIO142PB8

M2GL_MSIO142NB8

13

M2GL_MSIO158PB8

M2GL_MSIO157NB8

M2GL_MSIO143PB8

M2GL_MSIO143NB8

14

GND

M2GL_MSIO158NB8

M2GL_MSIO145PB8

M2GL_MSIO145NB8

15

M2GL_RSVD0

M2GL_RSVD1

GND

GND

16

GND

M2GL_RSVD2

M2GL_UART_TX

M2GL_JTAG_TRSTB

17

RSVD

M2GL_RSVD3

M2GL_UART_RX

M2GL_WDOG_OUT

18

GND

RSVD

M2GL_UART_DE

GND

19

RSVD

RSVD

M2GL_UART_RE_B

GND

20

GND

RSVD

RSVD(PUDC_B_503)

GND

21

IO_L8P_302

IO_L8N_302

MODE0_503

MODE1_503

22

IO_L5N_HDGC_302

GND

MODE2_503

MODE3_503

23

IO_L9P_302

IO_L9N_302

ERROR_OUT_503

DONE_503

24

IO_L6N_HDGC_302

GND

GND

GND

25

IO_L10P_302

IO_L10N_302

LPD_MIO12_502

LPD_MIO13_502

26

IO_L7N_302

GND

LPD_MIO14_502

LPD_MIO15_502

27

IO_L18P_XCC_N6P0_703

IO_L18N_XCC_N6P1_703

LPD_MIO16_502

LPD_MIO17_502

28

IO_L12N_GC_XCC_N4P1_703

GND

LPD_MIO18_502

LPD_MIO19_502

29

IO_L19P_N6P2_703

IO_L19N_N6P3_703

LPD_MIO20_502

LPD_MIO21_502

30

IO_L13N_N4P3_703

GND

LPD_MIO22_502

LPD_MIO23_502

31

IO_L20P_N6P4_703

IO_L20N_N6P5_703

LPD_MIO24_502

LPD_MIO25_502

32

IO_L14N_N4P5_703

GND

GND

GND

33

IO_L21P_XCC_N7P0_703

IO_L21N_XCC_N7P1_703

RSVD

PMC_MIO37_501

34

IO_L15N_XCC_N5P1_703

GND

PMC_MIO38_501

PMC_MIO39_501

35

IO_L22P_N7P2_703

IO_L22N_N7P3_703

PMC_MIO40_501

PMC_MIO41_501

36

IO_L16N_N5P3_703

GND

PMC_MIO42_501

PMC_MIO43_501

37

IO_L23P_N7P4_703

IO_L23N_N7P5_703

PMC_MIO44_501

PMC_MIO45_501

38

IO_L17N_N5P5_703

GND

PMC_MIO46_501

PMC_MIO47_501

39

IO_L26P_N8P4_703

IO_L26N_N8P5_703

PMC_MIO48_501

PMC_MIO49_501

40

IO_L25P_N8P3_703

IO_L25N_N8P3_703

GND

GND
Table 3. Board to Board Connector Pin Layout (Columns J–K)
Pin
Number		 J K

1

VIN_5V0

VIN_5V0

2

VIN_5V0

VIN_5V0

3

VIN_5V0

VIN_5V0

4

GND

GND

5

M2GL_MSIO196PB5

M2GL_MSIO196NB5

6

M2GL_MSIO197PB5

M2GL_MSIO197NB5

7

M2GL_MSIO198PB5

M2GL_MSIO198NB5

8

M2GL_MSIO201PB5

M2GL_MSIO201NB5

9

M2GL_MSIO203PB5

M2GL_MSIO203NB5

10

M2GL_MSIO204PB5

M2GL_MSIO204NB5

11

M2GL_VDDI5_IN

M2GL_VDDI5_IN

12

M2GL_MSIO136PB8

M2GL_MSIO136NB8

13

M2GL_MSIO140PB8

M2GL_MSIO140NB8

14

M2GL_VDDI8_IN

M2GL_VDDI8_IN

15

RSV(M2GL_DEVRST_N)

M2GL_VDDI4_OUT

16

M2GL_JTAG_TCK

M2GL_JTAG_TDI

17

M2GL_JTAG_TDO

M2GL_JTAG_TMS

18

VDD_3V3_OUT

VDD_3V3_OUT

19

VDD_1V8_OUT

VDD_1V8_OUT

20

VDD_1V2_OUT

VDD_1V2_OUT

21

TCK_503

TDI_503

22

TDO_503

TMS_503

23

RSVD

VCCO_503_OUT

24

GND

GND

25

LPD_MIO0_502

LPD_MIO1_502

26

LPD_MIO2_502

LPD_MIO3_502

27

LPD_MIO4_502

LPD_MIO5_502

28

LPD_MIO6_502

LPD_MIO7_502

29

LPD_MIO8_502

LPD_MIO9_502

30

LPD_MIO10_502

LPD_MIO11_502

31

VCCO_502_IN

VCCO_502_IN

32

VCCO_502_PWREN

VCCO_502_PWREN

33

PMC_MIO12_500

PMC_MIO13_500

34

PMC_MIO14_500

PMC_MIO15_500

35

PMC_MIO16_500

PMC_MIO17_500

36

PMC_MIO18_500

PMC_MIO19_500

37

PMC_MIO20_500

PMC_MIO21_500

38

PMC_MIO22_500

PMC_MIO23_500

39

PMC_MIO24_500

PMC_MIO25_500

40

VCCO_500_501_OUT

VCCO_500_501_OUT

CON1 Pin Details

Table 4. Board-to-Board Connector Signal Details (A)
Pin
No.		 Signal Name Description Bank Power Domain Pull

A1

GTYP_REFCLKP0_103

Versal GTYP 0 REFCLKP0

Versal 103

- (GTYP Power)

-

A2

GND

GND

-

-

-

A3

GTYP_RXP0_103

Versal GTYP 0 RXP0

Versal 103

- (GTYP Power)

-

A4

GND

GND

-

-

-

A5

GTYP_RXP1_103

Versal GTYP 0 RXP1

Versal 103

- (GTYP Power)

-

A6

GND

GND

-

-

-

A7

GTYP_RXP2_103

Versal GTYP 0 RXP2

Versal 103

- (GTYP Power)

-

A8

GND

GND

-

-

-

A9

GTYP_RXP3_103

Versal GTYP 0 RXP3

Versal 103

- (GTYP Power)

-

A10

GND

GND

-

-

-

A11

GTYP_REFCLKP0_104

Versal GTYP 1 REFCLKP0

Versal 104

- (GTYP Power)

-

A12

GND

GND

-

-

-

A13

GTYP_RXP0_104

Versal GTYP 1 RXP0

Versal 104

- (GTYP Power)

-

A14

GND

GND

-

-

-

A15

GTYP_RXP1_104

Versal GTYP 1 RXP1

Versal 104

- (GTYP Power)

-

A16

GND

GND

-

-

-

A17

GTYP_RXP2_104

Versal GTYP 1 RXP2

Versal 104

- (GTYP Power)

-

A18

GND

GND

-

-

-

A19

GTYP_RXP3_104

Versal GTYP 1 RXP3

Versal 104

- (GTYP Power)

-

A20

GND

GND

-

-

-

A21

VCCO_302_IN

"Versal PL HDIO Bank Power Input + (1.8 V / 2.5V / 3.3V)"

Versal 302

-

10k PD

A22

IO_L0P_302

Versal PL HDIO L0P

Versal 302

VCCO_302_IN

-

A23

GND

GND

-

-

-

A24

IO_L1P_302

Versal PL HDIO L1P

Versal 302

VCCO_302_IN

-

A25

GND

GND

-

-

-

A26

IO_L2P_302

Versal PL HDIO L2P

Versal 302

VCCO_302_IN

-

A27

GND

GND

-

-

-

A28

IO_L0P_XCC_N0P0_703

Versal PL XPIO L0P_N0P0

Versal 703

VCCO_703_IN

-

A29

GND

GND

-

-

-

A30

IO_L1P_N0P2_703

Versal PL XPIO L1P_N0P2

Versal 703

VCCO_703_IN

-

A31

GND

GND

-

-

-

A32

IO_L2P_N0P4_703

Versal PL XPIO L2P_N0P4

Versal 703

VCCO_703_IN

-

A33

GND

GND

-

-

-

A34

IO_L3P_XCC_N1P0_703

Versal PL XPIO L3P_N1P0

Versal 703

VCCO_703_IN

-

A35

GND

GND

-

-

-

A36

IO_L4P_N1P2_703

Versal PL XPIO L4P_N1P2

Versal 703

VCCO_703_IN

-

A37

GND

GND

-

-

-

A38

IO_L5P_N1P4_703

Versal PL XPIO L5P_N1P4

Versal 703

VCCO_703_IN

-

A39

GND

GND

-

-

-

A40

VCCO_703_IN

"Versal PL XPIO Bank Power Input+ (1.0 V / 1.2 V / 1.35 V / 1.5 V)"

Versal 703

-

10k PD
Table 5. Board-to-Board Connector Signal Details (B)
Pin
No.		 Signal Name Description Bank Power Domain Pull

B1

GTYP_REFCLKN0_103

Versal GTYP 0 REFCLKN0

Versal 103

- (GTYP Power)

-

B2

GND

GND

-

-

-

B3

GTYP_RXN0_103

Versal GTYP 0 RXN0

Versal 103

- (GTYP Power)

-

B4

GND

GND

-

-

-

B5

GTYP_RXN1_103

Versal GTYP 0 RXN1

Versal 103

- (GTYP Power)

-

B6

GND

GND

-

-

-

B7

GTYP_RXN2_103

Versal GTYP 0 RXN2

Versal 103

- (GTYP Power)

-

B8

GND

GND

-

-

-

B9

GTYP_RXN3_103

Versal GTYP 0 RXN

Versal 103

- (GTYP Power)

-

B10

GND

GND

-

-

-

B11

GTYP_REFCLKN0_104

Versal GTYP 1 REFCLKN0

Versal 104

- (GTYP Power)

-

B12

GND

GND

-

-

-

B13

GTYP_RXN0_104

Versal GTYP 1 RXN0

Versal 104

- (GTYP Power)

-

B14

GND

GND

-

-

-

B15

GTYP_RXN1_104

Versal GTYP 1 RXN1

Versal 104

- (GTYP Power)

-

B16

GND

GND

-

-

-

B17

GTYP_RXN2_104

Versal GTYP 1 RXN2

Versal 104

- (GTYP Power)

-

B18

GND

GND

-

-

-

B19

GTYP_RXN3_104

Versal GTYP 1 RXN3

Versal 104

- (GTYP Power)

-

B20

GND

GND

-

-

-

B21

VCCO_302_IN

Versal PL HDIO Bank Power Input + (1.8 V / 2.5 V / 3.3 V)

Versal 302

-

10k PD

B22

IO_L0N_302

Versal PL HDIO L0N

Versal 302

VCCO_302_IN

-

B23

IO_L3P_302

Versal PL HDIO L3P

Versal 302

VCCO_302_IN

-

B24

IO_L1N_302

Versal PL HDIO L1N

Versal 302

VCCO_302_IN

-

B25

IO_L4P_302

Versal PL HDIO L4P

Versal 302

VCCO_302_IN

-

B26

IO_L2N_302

Versal PL HDIO L2N

Versal 302

VCCO_302_IN

-

B27

IO_L6P_GC_XCC_N2P0_703

Versal PL XPIO L6P_GC_XCC_N2P0

Versal 703

VCCO_703_IN

-

B28

IO_L0N_XCC_N0P1_703

Versal PL XPIO L0P_N0P0

Versal 703

VCCO_703_IN

-

B29

IO_L7P_N2P2_703

Versal PL XPIO L7P_N2P1

Versal 703

VCCO_703_IN

-

B30

IO_L1N_N0P3_703

Versal PL XPIO L1N_N0P3

Versal 703

VCCO_703_IN

-

B31

IO_L8P_N2P4_703

Versal PL XPIO L8P_N2P4

Versal 703

VCCO_703_IN

-

B32

IO_L2N_N0P5_703

Versal PL XPIO L2N_N0P5

Versal 703

VCCO_703_IN

-

B33

IO_L9P_GC_XCC_N3P0_703

Versal PL XPIO L9P_GC_XCC_N3P0

Versal 703

VCCO_703_IN

-

B34

IO_L3N_XCC_N1P1_703

Versal PL XPIO L3N_N1P1

Versal 703

VCCO_703_IN

-

B35

IO_L10P_N3P2_703

Versal PL XPIO L10P_N3P2

Versal 703

VCCO_703_IN

-

B36

IO_L4N_N1P3_703

Versal PL XPIO L4N_N1P3

Versal 703

VCCO_703_IN

-

B37

IO_L11P_N3P4_703

Versal PL XPIO L11P_N3P4

Versal 703

VCCO_703_IN

-

B38

IO_L5N_N1P5_703

Versal PL XPIO L5N_N1P5

Versal 703

VCCO_703_IN

-

B39

IO_L24P_GC_XCC_N8P0_703

Versal PL XPIO L24P_GC_XCC_N8P0

Versal 703

VCCO_703_IN

-

B40

VCCO_703_IN

Versal PL XPIO Bank power Input (1.0 V / 1.2 V / 1.35 V / 1.5 V)

Versal 703

-

10k PD
Table 6. Board-to-Board Connector Signal Details (C)
Pin
No.		 Signal Name Description Bank Power Domain Pull

C1

GND

GND

-

-

-

C2

GTYP_TXP0_103

Versal GTYP 0 TXP0

Versal 103

- (GTYP Power)

-

C3

GND

GND

-

-

-

C4

GTYP_TXP1_103

Versal GTYP 0 TXP1

Versal 103

- (GTYP Power)

-

C5

GND

GND

-

-

-

C6

GTYP_TXP2_103

Versal GTYP 0 TXP2

Versal 103

- (GTYP Power)

-

C7

GND

GND

-

-

-

C8

GTYP_TXP3_103

Versal GTYP 0 TXP3

Versal 103

- (GTYP Power)

-

C9

GND

GND

-

-

-

C10

GTYP_REFCLKP1_103

Versal GTYP 0 REFCLKP1

Versal 103

- (GTYP Power)

-

C11

GND

GND

-

-

-

C12

GTYP_TXP0_104

Versal GTYP 1 TXP0

Versal 104

- (GTYP Power)

-

C13

GND

GND

-

-

-

C14

GTYP_TXP1_104

Versal GTYP 1 TXP1

Versal 104

- (GTYP Power)

-

C15

GND

GND

-

-

-

C16

GTYP_TXP2_104

Versal GTYP 1 TXP2

Versal 104

- (GTYP Power)

-

C17

GND

GND

-

-

-

C18

GTYP_TXP3_104

Versal GTYP 1 TXP3

Versal 104

- (GTYP Power)

-

C19

GND

GND

-

-

-

C20

GTYP_REFCLKP1_104

Versal GTYP 1 REFCLKP1

Versal 104

- (GTYP Power)

-

C21

GND

GND

-

-

-

C22

GND

GND

-

-

-

C23

IO_L3N_302

Versal PL HDIO L3N

Versal 302

VCCO_302_IN

-

C24

GND

GND

-

-

-

C25

IO_L4N_302

Versal PL HDIO L4N

Versal 302

VCCO_302_IN

-

C26

GND

GND

-

-

-

C27

IO_L6N_GC_XCC_N2P1_703

Versal PL XPIO L6N_GC_XCC_N2P1

Versal 703

VCCO_703_IN

-

C28

GND

GND

-

-

-

C29

IO_L7N_N2P3_703

Versal PL XPIO L7N_N2P3

Versal 703

VCCO_703_IN

-

C30

GND

GND

-

-

-

C31

IO_L8N_N2P5_703

Versal PL XPIO L8N_N2P5

Versal 703

VCCO_703_IN

-

C32

GND

GND

-

-

-

C33

IO_L9N_GC_XCC_N3P1_703

Versal PL XPIO L9N_GC_XCC_N3P1

Versal 703

VCCO_703_IN

-

C34

GND

GND

-

-

-

C35

IO_L10N_N3P3_703

Versal PL XPIO L10N_N3P3

Versal 703

VCCO_703_IN

-

C36

GND

GND

-

-

-

C37

IO_L11N_N3P5_703

Versal PL XPIO L11P_N3P5

Versal 703

VCCO_703_IN

-

C38

GND

GND

-

-

-

C39

IO_L24N_GC_XCC_N8P1_703

Versal PL XPIO L24N_GC_XCC_N8P1

Versal 703

VCCO_703_IN

-

C40

VCCO_302_703_PWREN

Versal PL 302/703 Bank power enable output

-

VDD_1V8_OUT

-
Table 7. Board-to-Board Connector Signal Details (D)
Pin
No.		 Signal Name Description Bank Power Domain Pull

D1

GND

GND

-

-

-

D2

GTYP_TXN0_103

Versal GTYP 0 TXN0

Versal 103

- (GTYP Power)

-

D3

GND

GND

-

-

-

D4

GTYP_TXN1_103

Versal GTYP 0 TXN1

Versal 103

- (GTYP Power)

-

D5

GND

GND

-

-

-

D6

GTYP_TXN2_103

Versal GTYP 0 TXN2

Versal 103

- (GTYP Power)

-

D7

GND

GND

-

-

-

D8

GTYP_TXN3_103

Versal GTYP 0 TXN3

Versal 103

- (GTYP Power)

-

D9

GND

GND

-

-

-

D10

GTYP_REFCLKN1_103

Versal GTYP 0 REFCLKN1

Versal 103

- (GTYP Power)

-

D11

GND

GND

-

-

-

D12

GTYP_TXN0_104

Versal GTYP 1 TXN0

Versal 104

- (GTYP Power)

-

D13

GND

GND

-

-

-

D14

GTYP_TXN1_104

Versal GTYP 1 TXN1

Versal 104

- (GTYP Power)

-

D15

GND

GND

-

-

-

D16

GTYP_TXN2_104

Versal GTYP 1 TXN2

Versal 104

- (GTYP Power)

-

D17

GND

GND

-

-

-

D18

GTYP_TXN3_104

Versal GTYP 1 TXN4

Versal 104

- (GTYP Power)

-

D19

GND

GND

-

-

-

D20

GTYP_REFCLKN1_104

Versal GTYP 1 REFCLKN1

Versal 104

- (GTYP Power)

-

D21

GND

GND

-

-

-

D22

IO_L5P_HDGC_302

Versal PL HDIO L5P_HDGC

Versal 302

VCCO_302_IN

-

D23

GND

GND

-

-

-

D24

IO_L6P_HDGC_302

Versal PL HDIO L6P_HDGC

Versal 302

VCCO_302_IN

-

D25

GND

GND

-

-

-

D26

IO_L7P_302

Versal PL HDIO L7P

Versal 302

VCCO_302_IN

-

D27

GND

GND

-

-

-

D28

IO_L12P_GC_XCC_N4P0_703

Versal PL XPIO L12P_GC_XCC_N4P0

Versal 703

VCCO_703_IN

-

D29

GND

GND

-

-

-

D30

IO_L13P_N4P2_703

Versal PL XPIO L13P_N4P2

Versal 703

VCCO_703_IN

-

D31

GND

GND

-

-

-

D32

IO_L14P_N4P4_703

Versal PL XPIO L14P_N4P4

Versal 703

VCCO_703_IN

-

D33

GND

GND

-

-

-

D34

IO_L15P_XCC_N5P0_703

Versal PL XPIO L15P_XCC_N5P0

Versal 703

VCCO_703_IN

-

D35

GND

GND

-

-

-

D36

IO_L16P_N5P2_703

Versal PL XPIO L16P_N5P2

Versal 703

VCCO_703_IN

-

D37

GND

GND

-

-

-

D38

IO_L17P_N5P4_703

Versal PL XPIO L17P_N5P4

Versal 703

VCCO_703_IN

-

D39

GND

GND

-

-

-

D40

VCCO_302_703_PWREN

Versal PL 302/703 Bank power enable output

-

VDD_1V8_OUT

-
Table 8. Board-to-Board Connector Signal Details (E)
Pin
No.		 Signal Name Description Bank Power Domain Pull

E1

VCC_BATT_IN

Power input for the real-time clock (RTC)

-

-

-

E2

GND

GND

-

-

-

E3

VCC_BATT_IN

Power input for the real-time clock (RTC)

-

-

-

E4

GND

GND

-

-

-

E5

M2GL_MSIO222PB5

IGLOO2 MSIO 0 MSIO222PB5

IGLOO2 5

M2GL_VDDI5_IN

-

E6

GND

GND

-

-

-

E7

M2GL_MSIO228PB5

IGLOO2 MSIO 0 MSIO228PB5

IGLOO2 5

M2GL_VDDI5_IN

-

E8

GND

GND

-

-

-

E9

M2GL_MSIO230PB5

IGLOO2 MSIO 0 MSIO230PB5

IGLOO2 5

M2GL_VDDI5_IN

-

E10

GND

GND

-

-

-

E11

M2GL_MSIO156PB8

IGLOO2 MSIO 1 MSIO156PB8

IGLOO2 8

M2GL_VDDI8_IN

-

E12

GND

GND

-

-

-

E13

M2GL_MSIO158PB8

IGLOO2 MSIO 1 MSIO158PB8

IGLOO2 8

M2GL_VDDI8_IN

-

E14

GND

GND

-

-

-

E15

M2GL_RSVD0

Reserved

-

-

-

E16

GND

GND

-

-

-

E17

RSVD

Reserved

-

-

-

E18

GND

GND

-

-

-

E19

RSVD

Reserved

-

-

-

E20

GND

GND

-

-

-

E21

IO_L8P_302

Versal PL HDIO L8P

Versal 302

VCCO_302_IN

-

E22

IO_L5N_HDGC_302

Versal PL HDIO L5N_HDGC

Versal 302

VCCO_302_IN

-

E23

IO_L9P_302

Versal PL HDIO L9P

Versal 302

VCCO_302_IN

-

E24

IO_L6N_HDGC_302

Versal PL HDIO L6N_HDGC

Versal 302

VCCO_302_IN

-

E25

IO_L10P_302

Versal PL HDIO L10P

Versal 302

VCCO_302_IN

-

E26

IO_L7N_302

Versal PL HDIO L7N

Versal 302

VCCO_302_IN

-

E27

IO_L18P_XCC_N6P0_703

Versal PL XPIO L18P_XCC_N6P0

Versal 703

VCCO_703_IN

-

E28

IO_L12N_GC_XCC_N4P1_703

Versal PL XPIO L12N_GC_XCC_N4P1

Versal 703

VCCO_703_IN

-

E29

IO_L19P_N6P2_703

Versal PL XPIO L19P_N6P2

Versal 703

VCCO_703_IN

-

E30

IO_L13N_N4P3_703

Versal PL XPIO L13N_N4P3

Versal 703

VCCO_703_IN

-

E31

IO_L20P_N6P4_703

Versal PL XPIO L20P_N6P4

Versal 703

VCCO_703_IN

-

E32

IO_L14N_N4P5_703

Versal PL XPIO L14N_N4P5

Versal 703

VCCO_703_IN

-

E33

IO_L21P_XCC_N7P0_703

Versal PL XPIO L21P_XCC_N7P0

Versal 703

VCCO_703_IN

-

E34

IO_L15N_XCC_N5P1_703

Versal PL XPIO L15N_XCC_N5P1

Versal 703

VCCO_703_IN

-

E35

IO_L22P_N7P2_703

Versal PL XPIO L22P_Nl7P2

Versal 703

VCCO_703_IN

-

E36

IO_L16N_N5P3_703

Versal PL XPIO L16N_N5P3

Versal 703

VCCO_703_IN

-

E37

IO_L23P_N7P4_703

Versal PL XPIO L23P_N7P4

Versal 703

VCCO_703_IN

-

E38

IO_L17N_N5P5_703

Versal PL XPIO L17N_N5P5

Versal 703

VCCO_703_IN

-

E39

IO_L26P_N8P4_703

Versal PL XPIO L26P_N8P4

Versal 703

VCCO_703_IN

-

E40

IO_L25P_N8P2_703

Versal PL XPIO L25P_N8P2

Versal 703

VCCO_703_IN

-
Table 9. Board-to-Board Connector Signal Details (F)
Pin
No.		 Signal Name Description Bank Power Domain Pull

F1

GND

GND

-

-

-

F2

GND

GND

-

-

-

F3

GND

GND

-

-

-

F4

GND

GND

-

-

-

F5

M2GL_MSIO222NB5

IGLOO2 MSIO 0 MSIO222NB5

IGLOO2 5

M2GL_VDDI5_IN

-

F6

M2GL_MSIO226PB5

IGLOO2 MSIO 0 MSIO226PB5

IGLOO2 5

M2GL_VDDI5_IN

-

F7

M2GL_MSIO226NB5

IGLOO2 MSIO 0 MSIO226NB5

IGLOO2 5

M2GL_VDDI5_IN

-

F8

M2GL_MSIO228NB5

IGLOO2 MSIO 0 MSIO228NB5

IGLOO2 5

M2GL_VDDI5_IN

-

F9

M2GL_MSIO230NB5

IGLOO2 MSIO 0 MSIO230NB5

IGLOO2 5

M2GL_VDDI5_IN

-

F10

RSVD

Reserved

-

-

-

F11

M2GL_MSIO156NB8

IGLOO2 MSIO 1 MSIO156NB8

IGLOO2 8

M2GL_VDDI8_IN

-

F12

M2GL_MSIO157PB8

IGLOO2 MSIO 1 MSIO157PB8

IGLOO2 8

M2GL_VDDI8_IN

-

F13

M2GL_MSIO157NB8

IGLOO2 MSIO 1 MSIO157NB8

IGLOO2 8

M2GL_VDDI8_IN

-

F14

M2GL_MSIO158NB8

IGLOO2 MSIO 1 MSIO158NB8

IGLOO2 8

M2GL_VDDI8_IN

-

F15

M2GL_RSVD1

Reserved

-

-

-

F16

M2GL_RSVD2

Reserved

-

-

-

F17

M2GL_RSVD3

Reserved

-

-

-

F18

RSVD

Reserved

-

-

-

F19

RSVD

Reserved

-

-

-

F20

RSVD

Reserved

-

-

-

F21

IO_L8N_302

Versal PL HDIO L8N

Versal 302

VCCO_302_IN

-

F22

GND

GND

-

-

-

F23

IO_L9N_302

Versal PL HDIO L9N

Versal 302

VCCO_302_IN

-

F24

GND

GND

-

-

-

F25

IO_L10N_302

Versal PL HDIO L10N

Versal 302

VCCO_302_IN

-

F26

GND

GND

-

-

-

F27

IO_L18N_XCC_N6P1_703

Versal PL XPIO L18N_XCC_N6P1

Versal 703

VCCO_703_IN

-

F28

GND

GND

-

-

-

F29

IO_L19N_N6P3_703

Versal PL XPIO L19N_N6P3

Versal 703

VCCO_703_IN

-

F30

GND

GND

-

-

-

F31

IO_L20N_N6P5_703

Versal PL XPIO L20N_N6P5

Versal 703

VCCO_703_IN

-

F32

GND

GND

-

-

-

F33

IO_L21N_XCC_N7P1_703

Versal PL XPIO L21N_XCC_N7P1

Versal 703

VCCO_703_IN

-

F34

GND

GND

-

-

-

F35

IO_L22N_N7P3_703

Versal PL XPIO L22N_N7P3

Versal 703

VCCO_703_IN

-

F36

GND

GND

-

-

-

F37

IO_L23N_N7P5_703

Versal PL XPIO L23N_N7P5

Versal 703

VCCO_703_IN

-

F38

GND

GND

-

-

-

F39

IO_L26N_N8P5_703

Versal PL XPIO L26N_N8P5

Versal 703

VCCO_703_IN

-

F40

IO_L25N_N8P3_703

Versal PL XPIO L25N_N8P3

Versal 703

VCCO_703_IN

-
Table 10. Board-to-Board Connector Signal Details (G)
Pin
No.		 Signal Name Description Bank Power Domain Pull

G1

VIN_5V0

Main power input

-

-

-

G2

VIN_5V0

Main power input

-

-

-

G3

VIN_5V0

Main power input

-

-

-

G4

GND

GND

-

-

-

G5

M2GL_MSIO208PB5

IGLOO2 MSIO 0 MSIO208PB5

IGLOO2 5

M2GL_VDDI5_IN

-

G6

M2GL_MSIO209PB5

IGLOO2 MSIO 0 MSIO209PB5

IGLOO2 5

M2GL_VDDI5_IN

-

G7

M2GL_MSIO212PB5

IGLOO2 MSIO 0 MSIO212PB5

IGLOO2 5

M2GL_VDDI5_IN

-

G8

M2GL_MSIO213PB5

IGLOO2 MSIO 0 MSIO213PB5

IGLOO2 5

M2GL_VDDI5_IN

-

G9

M2GL_MSIO216PB5

IGLOO2 MSIO 0 MSIO216PB5

IGLOO2 5

M2GL_VDDI5_IN

-

G10

M2GL_MSIO221PB5

IGLOO2 MSIO 0 MSIO221PB5

IGLOO2 5

M2GL_VDDI5_IN

-

G11

GND

GND

-

-

-

G12

M2GL_MSIO142PB8

IGLOO2 MSIO 1 MSIO142PB8

IGLOO2 8

M2GL_VDDI8_IN

-

G13

M2GL_MSIO143PB8

IGLOO2 MSIO 1 MSIO143PB8

IGLOO2 8

M2GL_VDDI8_IN

-

G14

M2GL_MSIO145PB8

IGLOO2 MSIO 1 MSIO145PB8

IGLOO2 8

M2GL_VDDI8_IN

-

G15

GND

GND

-

-

-

G16

M2GL_UART_TX

IGLOO2 UART TX output

IGLOO2 3

VDD_1V8_OUT

-

G17

M2GL_UART_RX

IGLOO2 UART RX input

IGLOO2 3

VDD_1V8_OUT

10k PU

G18

M2GL_UART_DE

IGLOO2 UART TX enable output

IGLOO2 3

VDD_1V8_OUT

-

G19

M2GL_UART_RE_B

IGLOO2 UART RX enable output

IGLOO2 3

VDD_1V8_OUT

10k PU

G20

RSVD(PUDC_B_503)

Reserved

Versal 503

VCCO_503_OUT

1k PU

G21

MODE0_503

Versal Boot Modesignal bit 0 input

Versal 503

VCCO_503_OUT

4.7k PU

G22

MODE2_503

Versal Boot Modesignal bit 2 input

Versal 503

VCCO_503_OUT

4.7k PU

G23

ERROR_OUT_503

Versal Error output

Versal 503

VCCO_503_OUT

4.7k PU

G24

GND

GND

-

-

-

G25

LPD_MIO12_502

Versal LPD MIO bit 12

Versal 502

VCCO_502_IN

-

G26

LPD_MIO14_502

Versal LPD MIO bit 14

Versal 502

VCCO_502_IN

-

G27

LPD_MIO16_502

Versal LPD MIO bit 16

Versal 502

VCCO_502_IN

-

G28

LPD_MIO18_502

Versal LPD MIO bit 18

Versal 502

VCCO_502_IN

-

G29

LPD_MIO20_502

Versal LPD MIO bit 20

Versal 502

VCCO_502_IN

-

G30

LPD_MIO22_502

Versal LPD MIO bit 22

Versal 502

VCCO_502_IN

-

G31

LPD_MIO24_502

Versal LPD MIO bit 24

Versal 502

VCCO_502_IN

-

G32

GND

GND

-

-

-

G33

RSVD

Reserved

-

-

-

G34

PMC_MIO38_501

Versal LPD MIO bit 38

Versal 501

VCCO_500_501_OUT

-

G35

PMC_MIO40_501

Versal LPD MIO bit 40

Versal 501

VCCO_500_501_OUT

-

G36

PMC_MIO42_501

Versal LPD MIO bit 42

Versal 501

VCCO_500_501_OUT

-

G37

PMC_MIO44_501

Versal LPD MIO bit 44

Versal 501

VCCO_500_501_OUT

-

G38

PMC_MIO46_501

Versal LPD MIO bit 46

Versal 501

VCCO_500_501_OUT

-

G39

PMC_MIO48_501

Versal LPD MIO bit 48

Versal 501

VCCO_500_501_OUT

-

G40

GND

GND

-

-

-
Table 11. Board-to-Board Connector Signal Details (H)
Pin
No.		 Signal Name Description Bank Power Domain Pull

H1

VIN_5V0

Main power input

-

-

-

H2

VIN_5V0

Main power input

-

-

-

H3

VIN_5V0

Main power input

-

-

-

H4

GND

GND

-

-

-

H5

M2GL_MSIO208NB5

IGLOO2 MSIO 0 MSIO208NB5

IGLOO2 5

M2GL_VDDI5_IN

-

H6

M2GL_MSIO209NB5

IGLOO2 MSIO 0 MSIO209NB5

IGLOO2 5

M2GL_VDDI5_IN

-

H7

M2GL_MSIO212NB5

IGLOO2 MSIO 0 MSIO212NB5

IGLOO2 5

M2GL_VDDI5_IN

-

H8

M2GL_MSIO213NB5

IGLOO2 MSIO 0 MSIO213NB5

IGLOO2 5

M2GL_VDDI5_IN

-

H9

M2GL_MSIO216NB5

IGLOO2 MSIO 0 MSIO216NB5

IGLOO2 5

M2GL_VDDI5_IN

-

H10

M2GL_MSIO221NB5

IGLOO2 MSIO 0 MSIO221NB5

IGLOO2 5

M2GL_VDDI5_IN

-

H11

GND

GND

-

-

-

H12

M2GL_MSIO142NB8

IGLOO2 MSIO 1 MSIO142NB8

IGLOO2 8

M2GL_VDDI8_IN

-

H13

M2GL_MSIO143NB8

IGLOO2 MSIO 1 MSIO143NB8

IGLOO2 8

M2GL_VDDI8_IN

-

H14

M2GL_MSIO145NB8

IGLOO2 MSIO 1 MSIO145NB8

IGLOO2 8

M2GL_VDDI8_IN

-

H15

GND

GND

-

-

-

H16

M2GL_JTAG_TRSTB

IGLOO2 JTAG TRSTB input

IGLOO2 4

M2GL_VDDI4_OUT

1k PD

H17

M2GL_WDOG_OUT

IGLOO2 JTAG WDOG_OUT output

IGLOO2 3

VDD_1V8_OUT

-

H18

GND

GND

-

-

-

H19

GND

GND

-

-

-

H20

GND

GND

-

-

-

H21

MODE1_503

Versal Boot Modesignal bit 1 input

Versal 503

VCCO_503_OUT

4.7k PU

H22

MODE3_503

Versal Boot Modesignal bit 3 input

Versal 503

VCCO_503_OUT

4.7k PU

H23

DONE_503

Versal FPGA Configuration Done output

Versal 503

VCCO_503_OUT

4.7k PU

H24

GND

GND

-

-

-

H25

LPD_MIO13_502

Versal LPD MIO bit 13

Versal 502

VCCO_502_IN

-

H26

LPD_MIO15_502

Versal LPD MIO bit 15

Versal 502

VCCO_502_IN

-

H27

LPD_MIO17_502

Versal LPD MIO bit 17

Versal 502

VCCO_502_IN

-

H28

LPD_MIO19_502

Versal LPD MIO bit 19

Versal 502

VCCO_502_IN

-

H29

LPD_MIO21_502

Versal LPD MIO bit 21

Versal 502

VCCO_502_IN

-

H30

LPD_MIO23_502

Versal LPD MIO bit 23

Versal 502

VCCO_502_IN

-

H31

LPD_MIO25_502

Versal LPD MIO bit 25

Versal 502

VCCO_502_IN

-

H32

GND

GND

-

-

-

H33

PMC_MIO37_501

Versal PMC MIO bit 37

Versal 501

VCCO_500_501_OUT

-

H34

PMC_MIO39_501

Versal PMC MIO bit 39

Versal 501

VCCO_500_501_OUT

-

H35

PMC_MIO41_501

Versal PMC MIO bit 41

Versal 501

VCCO_500_501_OUT

-

H36

PMC_MIO43_501

Versal PMC MIO bit 43

Versal 501

VCCO_500_501_OUT

-

H37

PMC_MIO45_501

Versal PMC MIO bit 45

Versal 501

VCCO_500_501_OUT

-

H38

PMC_MIO47_501

Versal PMC MIO bit 47

Versal 501

VCCO_500_501_OUT

-

H39

PMC_MIO49_501

Versal PMC MIO bit 49

Versal 501

VCCO_500_501_OUT

-

H40

GND

GND

-

-

-
Table 12. Board-to-Board Connector Signal Details (J)
Pin
No.		 Signal Name Description Bank Power Domain Pull

J1

VIN_5V0

Main power input

-

-

-

J2

VIN_5V0

Main power input

-

-

-

J3

VIN_5V0

Main power input

-

-

-

J4

GND

GND

-

-

-

J5

M2GL_MSIO196PB5

IGLOO2 MSIO 0 MSIO196PB5

IGLOO2 5

M2GL_VDDI5_IN

-

J6

M2GL_MSIO197PB5

IGLOO2 MSIO 0 MSIO197PB5

IGLOO2 5

M2GL_VDDI5_IN

-

J7

M2GL_MSIO198PB5

IGLOO2 MSIO 0 MSIO198PB5

IGLOO2 5

M2GL_VDDI5_IN

-

J8

M2GL_MSIO201PB5

IGLOO2 MSIO 0 MSIO201PB5

IGLOO2 5

M2GL_VDDI5_IN

-

J9

M2GL_MSIO203PB5

IGLOO2 MSIO 0 MSIO203PB5

IGLOO2 5

M2GL_VDDI5_IN

-

J10

M2GL_MSIO204PB5

IGLOO2 MSIO 0 MSIO204PB5

IGLOO2 5

M2GL_VDDI5_IN

-

J11

M2GL_VDDI5_IN

IGLOO2 Bank 5 IO power input

IGLOO2 5

-

10k PD

J12

M2GL_MSIO136PB8

IGLOO2 MSIO 1 MSIO136PB8

IGLOO2 8

M2GL_VDDI8_IN

-

J13

M2GL_MSIO140PB8

IGLOO2 MSIO 1 MSIO140PB8

IGLOO2 8

M2GL_VDDI8_IN

-

J14

M2GL_VDDI8_IN

IGLOO2 Bank 8 IO power input

IGLOO2 8

-

10k PD

J15

RSVD(M2GL_DEVRST_N)

IGLOO2 DEVRESET input

-

- (3.3V)

10k PU

J16

M2GL_JTAG_TCK

IGLOO2 JTAG TCK input

IGLOO2 4

M2GL_VDDI4_OUT

1k PD

J17

M2GL_JTAG_TDO

IGLOO2 JTAG TDO output

IGLOO2 4

M2GL_VDDI4_OUT

-

J18

VDD_3V3_OUT

Versal/IGLOO2 3.3V power output

-

-

-

J19

VDD_1V8_OUT

Versal/IGLOO2 1.8V power output

-

-

-

J20

VDD_1V2_OUT

Versal/IGLOO2 1.2 V power output

-

-

-

J21

TCK_503

Versal JTAG TCK input

Versal 503

VCCO_503_OUT

4.7k PU

J22

TDO_503

Versal JTAG TDO output

Versal 503

VCCO_503_OUT

4.7k PU

J23

RSVD

-

-

-

-

J24

GND

GND

-

-

-

J25

LPD_MIO0_502

Versal LPD MIO bit 0

Versal 502

VCCO_502_IN

-

J26

LPD_MIO2_502

Versal LPD MIO bit 2

Versal 502

VCCO_502_IN

-

J27

LPD_MIO4_502

Versal LPD MIO bit 4

Versal 502

VCCO_502_IN

-

J28

LPD_MIO6_502

Versal LPD MIO bit 6

Versal 502

VCCO_502_IN

-

J29

LPD_MIO8_502

Versal LPD MIO bit 8

Versal 502

VCCO_502_IN

-

J30

LPD_MIO10_502

Versal LPD MIO bit 10

Versal 502

VCCO_502_IN

-

J31

VCCO_502_IN

Versal LPD MIO Bank power Input

Versal 502

-

10k PD

J32

VCCO_502_PWREN

Versal LPD MIO Bank power enable output

-

VDD_1V8_OUT

-

J33

PMC_MIO12_500

Versal PMC MIO 0 bit 12

Versal 500

VCCO_500_501_OUT

-

J34

PMC_MIO14_500

Versal PMC MIO 0 bit 14

Versal 500

VCCO_500_501_OUT

-

J35

PMC_MIO16_500

Versal PMC MIO 0 bit 16

Versal 500

VCCO_500_501_OUT

-

J36

PMC_MIO18_500

Versal PMC MIO 0 bit 18

Versal 500

VCCO_500_501_OUT

-

J37

PMC_MIO20_500

Versal PMC MIO 0 bit 20

Versal 500

VCCO_500_501_OUT

-

J38

PMC_MIO22_500

Versal PMC MIO 0 bit 22

Versal 500

VCCO_500_501_OUT

-

J39

PMC_MIO24_500

Versal PMC MIO 0 bit 24

Versal 500

VCCO_500_501_OUT

-

J40

VCCO_500_501_OUT

Versal Bank 500/501 1.8V IO power output

-

-

-
Table 13. Board-to-Board Connector Signal Details (K)
Pin
No.		 Signal Name Description Bank Power Domain Pull

K1

VIN_5V0

Main power input

-

-

-

K2

VIN_5V0

Main power input

-

-

-

K3

VIN_5V0

Main power input

-

-

-

K4

GND

GND

-

-

-

K5

M2GL_MSIO196NB5

IGLOO2 MSIO 0 MSIO196NB5

IGLOO2 5

M2GL_VDDI5_IN

-

K6

M2GL_MSIO197NB5

IGLOO2 MSIO 0 MSIO197NB5

IGLOO2 5

M2GL_VDDI5_IN

-

K7

M2GL_MSIO198NB5

IGLOO2 MSIO 0 MSIO198NB5

IGLOO2 5

M2GL_VDDI5_IN

-

K8

M2GL_MSIO201NB5

IGLOO2 MSIO 0 MSIO201NB5

IGLOO2 5

M2GL_VDDI5_IN

-

K9

M2GL_MSIO203NB5

IGLOO2 MSIO 0 MSIO203NB5

IGLOO2 5

M2GL_VDDI5_IN

-

K10

M2GL_MSIO204NB5

IGLOO2 MSIO 0 MSIO204NB5

IGLOO2 5

M2GL_VDDI5_IN

-

K11

M2GL_VDDI5_IN

IGLOO2 Bank 5 IO power Input

-

-

10k PD

K12

M2GL_MSIO136NB8

IGLOO2 MSIO 1 MSIO136NB8

IGLOO2 8

M2GL_VDDI8_IN

-

K13

M2GL_MSIO140NB8

IGLOO2 MSIO 1 MSIO140NB8

IGLOO2 8

M2GL_VDDI8_IN

-

K14

M2GL_VDDI8_IN

IGLOO2 Bank 8 IO power Input

-

-

10k PD

K15

M2GL_VDDI4_OUT

IGLOO2 Bank 4 IO power output

-

-

-

K16

M2GL_JTAG_TDI

IGLOO2 JTAG TDI input

IGLOO2 4

M2GL_VDDI4_OUT

-

K17

M2GL_JTAG_TMS

IGLOO2 JTAG TMS input

IGLOO2 4

M2GL_VDDI4_OUT

-

K18

VDD_3V3_OUT

Versal/IGLOO2 3.3V power output

-

-

-

K19

VDD_1V8_OUT

Versal/IGLOO2 1.8V power output

-

-

-

K20

VDD_1V2_OUT

Versal/IGLOO2 1.2 V power output

-

-

-

K21

TDI_503

Versal JTAG TDI input

Versal 503

VCCO_503_OUT

4.7k PU

K22

TMS_503

Versal JTAG TMS input

Versal 503

VCCO_503_OUT

4.7k PU

K23

VCCO_503_OUT

Versal Bank 503 1.8V IO power output

-

-

-

K24

GND

GND

-

-

-

K25

LPD_MIO1_502

Versal LPD MIO bit 1

Versal 502

VCCO_502_IN

-

K26

LPD_MIO3_502

Versal LPD MIO bit 3

Versal 502

VCCO_502_IN

-

K27

LPD_MIO5_502

Versal LPD MIO bit 5

Versal 502

VCCO_502_IN

-

K28

LPD_MIO7_502

Versal LPD MIO bit 7

Versal 502

VCCO_502_IN

-

K29

LPD_MIO9_502

Versal LPD MIO bit 9

Versal 502

VCCO_502_IN

-

K30

LPD_MIO11_502

Versal LPD MIO bit 11

Versal 502

VCCO_502_IN

-

K31

VCCO_502_IN

Versal LPD MIO Bank power Input

Versal 502

VCCO_502_IN

10k PD

K32

VCCO_502_PWREN

Versal LPD MIO Bank power enable output

-

VDD_1V8_OUT

-

K33

PMC_MIO13_500

Versal PMC MIO 0 bit 13

Versal 500

VCCO_500_501_OUT

-

K34

PMC_MIO15_500

Versal PMC MIO 0 bit 15

Versal 500

VCCO_500_501_OUT

-

K35

PMC_MIO17_500

Versal PMC MIO 0 bit 17

Versal 500

VCCO_500_501_OUT

-

K36

PMC_MIO19_500

Versal PMC MIO 0 bit 19

Versal 500

VCCO_500_501_OUT

-

K37

PMC_MIO21_500

Versal PMC MIO 0 bit 21

Versal 500

VCCO_500_501_OUT

-

K38

PMC_MIO23_500

Versal PMC MIO 0 bit 23

Versal 500

VCCO_500_501_OUT

-

K39

PMC_MIO25_500

Versal PMC MIO 0 bit 25

Versal 500

VCCO_500_501_OUT

-

K40

VCCO_500_501_OUT

Versal Bank 500/501 1.8V IO power output

-

-

-

JTAG Signals

The SC-OBC Module V1 provides JTAG signals for programming and debugging the two onboard FPGAs. Direct access to the JTAG signals for each FPGA is available via the 400-pin board-to-board connector.

The following table shows how the Versal and IGLOO2 JTAG signals are assigned to each pin on the board-to-board connector. For details, refer to SC-ESP-00086.

JTAG Signal Versal JTAG Pin IGLOO2 JTAG Pin

JTAG TCK

J21

J16

JTAG TMS

K22

K17

JTAG TDI

K21

K16

JTAG TDO

J22

J17

JTAG TRSTB

-

H16

Versal Boot Mode Signal

The Versal device on the SC-OBC Module V1 determines its boot method by reading the state of the Boot Mode pin after power-up.

In normal operation, the SC-OBC Module V1 is designed to store software in the onboard NOR flash memory and eMMC and boot from there. However, to facilitate initial development, software can also be stored on an SD card on the carrier board. This allows convenient use of the SD card in development scenarios requiring frequent software updates.

All four bits of the Boot Mode signal are wired to the board-to-board connector, but not all combinations of these bits are supported.

MODE [3:0] pin Boot Interface Usable on SC-OBC module V1

0000

JTAG

Yes

1010

SelectMAP

No

1000

OSPI

No

0001

QSPI24

No

0010

QSPI32

Yes

0110

eMMC1 v4.51

Yes (not recommended)

0011

SD0 v3.0

Yes

0101

SD1 v2.0

No

1110

SD1 v3.0

No

Versal PMC MIO 0/1, LPD MIO

On the SC-OBC Module V1, the PMC MIO 0/1 and LPD MIO located within the Versal device’s PMC (Platform Management Controller) and LPD (Low Power Domain) are provided as LVCMOS I/O buffers available to the user. These I/O pins are multiplexed with multiple peripherals implemented within the PMC and LPD, and their functions can be selected via software configuration.

Due to implementation constraints on the SC-OBC Module V1, the I/O voltage for PMC MIO 0/1 is fixed at 1.8 V. In contrast, the LPD MIO allows flexible selection of I/O voltage by supplying the bank power (VCCO_502) via the board-to-board connector.

The table below lists each MIO available to the user and the functions assignable to each.

Table 14. Types of User-Accessible MIOs
MIO Description IO Bank IO Voltage [V]

Versal PMC MIO 0

Platform Management MIO[25:12]

500

1.8

Versal PMC MIO 1

Platform Management MIO[49:37]

501

1.8

Versal LPD MIO

Low Power Domain MIO [25:0]

502

1.8/2.5/3.3
Table 15. Versal PMC MIO 0 (Bank 500) Pin Assignments
SD/eMMC0 - D0 D1 D2 D3 PWR CLK SEL DIRC DIR0 DIR1 CMD CD WP

Tamper Trig

TRIG

TRIG

-

-

-

-

-

-

-

-

TRIG

TRIG

-

-

PMC I2C

-

-

SCL

SDA

-

-

SCL

SDA

-

-

SCL

SDA

-

-

PMC GPIO

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GEM0 RGMII

-

-

-

-

-

-

-

-

-

-

-

-

-

-

GEM1 RGMII

-

-

-

-

-

-

-

-

-

-

-

-

-

-

GEM MDIO

-

-

-

-

-

-

-

-

-

-

-

-

-

-

GEM TSU

-

-

-

-

-

-

-

-

-

-

-

-

-

-

CAN FD0

RX

TX

-

-

RX

TX

-

-

RX

TX

-

-

-

-

CAN FD1

-

-

TX

RX

-

-

TX

RX

-

-

TX

RX

-

-

LPD I2C0

-

-

SCL

SDA

-

-

SCL

SDA

-

-

SCL

SDA

-

-

LPD I2C1

SCL

SDA

-

-

SCL

SDA

-

-

SCL

SDA

-

-

-

-

SYSMON I2C

-

SCL

SDA

SMB

-

-

SCL

SDA

SMB

-

-

SCL

SDA

SMB

PCIe Resets

-

-

-

-

-

-

-

-

-

-

-

-

RST0

RST1

SPI0

SCLK

CS2

CS1

CS0

MISO

MOSI

-

-

-

-

-

-

-

-

Trace Port

-

-

-

-

-

-

-

-

-

-

-

-

-

-

TTC

-

-

-

-

CLK3

WA3

CLK2

WA2

CLK1

A1

CLK0

WA0

-

-

UART0

-

-

-

-

RXD

TXD

CST

RTS

-

-

-

-

-

-

UART1

TXD

RXD

RTS

CTS

-

-

-

-

TXD

RXD

RTS

CTS

-

-

USB2.0

-

RST

D0

D1

D2

D3

CLK

D4

D5

D6

D7

DIR

STP

NXT

LPD SWDT

CLK

RST1

PEND

INT

WS0

WS1

-

-

-

-

-

-

-

-

FPD SWDT

-

-

-

-

-

-

CLK

RST1

PEND

PEND

WS0

WS1

-

-
Table 16. Versal PMC MIO 1 (Bank 501) Pin Assignments
MIO Pins 37 38 39 40 41 42 43 44 45 46 47 48 49

SD/eMMC0

WP

CLK

CD

CMD

D0

D1

D2

D3

SEL

DIRC

DIR0

DIR1

PWR

Tamper Trig

TRIG

-

-

-

-

-

-

-

-

-

-

-

-

PMC I2C

SCL

SDA

-

-

SCL

SDA

-

-

SCL

SDA

-

-

PMC GPIO

37

38

39

40

41

42

43

44

45

46

47

48

49

GEM0 RGMII

-

-

-

-

-

-

-

-

-

-

-

-

-

GEM1 RGMII

-

TXCLK

TXD0

TXD1

TXD2

TXD3

TXCTL

RXCLK

RXD0

RXD1

RXD2

RXD3

RXCTL

GEM MDIO

-

-

-

-

-

-

-

-

-

-

-

-

-

GEM TSU

-

-

-

-

-

-

-

-

-

-

-

-

-

CAN FD0

-

RX

TX

-

-

RX

TX

-

-

RX

TX

-

-

CAN FD1

-

-

-

TX

RX

-

-

TX

RX

-

-

-

-

LPD I2C0

-

SCL

SDA

-

-

SCL

SDA

-

-

SCL

SDA

-

-

LPD I2C1

-

-

-

SCL

SDA

-

-

SCL

SDA

-

-

SCL

SDA

SYSMON I2C

-

-

SCL

SDA

SMB

-

-

SCL

SDA

SMB

-

-

-

PCIe Resets

-

RST0

RST1

-

-

-

-

-

-

-

-

-

-

SPI0

-

SCLK

CS2

CS1

CS0

MISO

MOSI

-

-

-

-

-

-

Trace Port

-

-

-

-

-

-

-

-

-

-

-

-

-

TTC

-

CLK1

WA1

CLLK0

WA0

CLK3

WA3

CLK2

WA2

CLK1

WA1

CLK0

WA0

UART0

-

-

-

-

-

RXD

TXD

CTS

RTS

-

-

-

-

UART1

-

TXD

RXD

RTS

CTS

-

-

-

-

TXD

RXD

RTS

CTS

USB2.0

-

-

-

-

-

-

-

-

-

-

-

-

-

LPD SWDT

-

CLK

RST1

PEND

INT

WS0

WS1

-

-

-

-

-

-

FPD SWDT

-

-

-

-

-

-

-

CLK

RST

PEND

INT

WS0

WS1
Table 17. Versal LPD MIO (Bank 502) Pin Assignments
MIO Pins 0 1 2 3 4 5 6 7 8 9 10 11 12

SD/eMMC0

-

-

-

-

-

-

-

-

-

-

-

-

-

Tamper Trig

-

-

-

-

-

-

-

-

-

-

-

-

-

PMC I2C

-

-

-

-

-

-

-

-

-

-

-

-

-

LPD GPIO

0

1

2

3

4

5

6

7

8

9

10

11

12

GEM0 RGMII

TXCLK

TXD0

TXD1

TXD2

TXD3

TXCTL

RXCLK

RXD0

RXD1

RXD2

RXD3

RXCTL

-

GEM1 RGMII

-

-

-

-

-

-

-

-

-

-

-

-

TXCLK

GEM MDIO

-

-

-

-

-

-

-

-

-

-

-

-

-

GEM TSU

-

-

-

-

-

-

-

-

-

-

-

-

-

CAN FD0

-

-

RX

TX

-

-

RX

TX

-

-

-

RX

TX

CAN FD1

TX

RX

-

-

TX

RX

-

-

TX

RX

-

-

TX

LPD I2C0

-

-

SCL

SDA

-

-

SCL

SDA

-

-

SCL

SDA

-

LPD I2C1

SCL

SDA

-

-

SCL

SDA

-

-

SCL

SDA

-

-

SCL

SYSMON I2C

SCL

SDA

SMB

-

SCL

SDA

SMB

-

SCL

SDA

SMB

-

PCIe Resets

-

-

-

-

-

-

-

-

-

-

-

-

-

SPI0

SCLK

CS2

CS1

CS0

MISO

MOSI

-

-

-

-

-

-

SCLK

Trace Port

-

-

CTL

D0

D1

D2

CLK

D3

D4

D5

D6

D7

D8

TTC

CLK3

WA3

CLK2

WA2

CLK1

WA1

CLK0

WA0

CLK3

WA3

CLK2

WA2

CLK1

UART0

RXD

TXD

CTS

RTS

-

-

-

-

RXD

TXD

CTS

RTS

-

UART1

-

-

-

-

TXD

RXD

RTS

CTS

-

-

-

-

TXD

USB2.0

-

-

-

-

-

-

-

-

-

-

-

-

-

LPD SWDT

CLK

RST1

PEND

INT

WS0

WS1

-

-

-

-

-

-

CLK

FPD SWDT

-

-

-

-

-

-

CLK

RST1

PEND

INT

WS0

WS1

-
Table 18. Versal LPD MIO (Bank 502) Pin Assignments
MIO Pins 13 14 15 16 17 18 19 20 21 22 23 24 25

SD/eMMC0

-

-

-

-

-

-

-

-

-

-

-

-

-

Tamper Trig

-

-

-

-

-

-

-

-

-

-

-

-

-

PMC I2C

-

-

-

-

-

-

-

-

-

-

-

-

-

LPD GPIO

13

14

15

16

17

18

19

20

21

22

23

24

25

GEM0 RGMII

-

-

-

-

-

-

-

-

-

-

-

-

-

GEM1 RGMII

TXD0

TXD1

TXD2

TXD3

TXCTL

RXCLK

RXD0

RXD1

RXD2

RXD3

RXCTL

-

-

GEM MDIO

-

-

-

-

-

-

-

-

-

-

-

CLK

DATA

GEM TSU

-

-

-

-

-

-

-

-

-

-

-

CLK

CLK

CAN FD0

-

RX

TX

-

-

RX

TX

-

-

RX

TX

-

-

CAN FD1

RX

-

-

TX

RX

-

-

TX

RX

-

-

TX

RX

LPD I2C0

-

SCL

SDA

-

-

SCL

SDA

-

-

SCL

SDA

-

-

LPD I2C1

SDA

-

-

SCL

SDA

-

-

SCL

SDA

-

-

SCL

SDA

SYSMON I2C

SCL

SDA

SMB

-

-

SCL

SDA

SMB

-

-

SCL

SDA

SMB

PCIe Resets

-

-

-

-

-

RST0

RST1

-

-

-

-

-

-

SPI0

CS2

CS1

CS0

MISO

MOSI

-

-

-

-

-

-

-

-

Trace Port

D9

-

-

-

-

D10

D11

D12

D13

D14

D15

-

-

TTC

WA1

CLK0

WA0

CLK3

WA3

CLK2

WA2

CLK1

WA1

CLK0

WA0

-

-

UART0

-

-

-

RXD

TXD

CTS

RTS

-

-

-

-

-

-

UART1

RXD

RTS

CTS

-

-

-

-

TXD

RXD

RTS

CTS

-

-

USB2.0

-

-

-

-

-

-

-

-

-

-

-

-

-

LPD SWDT

RST1

PEND

INT

WS0

WS1

-

-

-

-

-

-

-

-

FPD SWDT

-

-

-

-

-

CLK

RST1

PEND

INT

WS0

WS1

-

-

Versal PL HDIO

Versal PL HDIO signals are connected to the HDIO on the programmable logic side of the Versal device and are made accessible to the user. HDIO (High-Density I/O) includes resources supporting low-speed SDR and DDR interfaces. These I/Os support standards compatible with 1.8 V, 2.5 V, and 3.3 V bank voltages.

The Versal device on the SC-OBC Module V1 has 22 HDIO signals, all of which are available to the user. To use the Versal PL HDIO, the user must supply bank power from the carrier board via VCCO_302, selecting one of the bank voltages supported by the Versal.

Versal PL XPIO

Versal PL XPIO signals connect to the XPIO on the programmable logic side of the Versal device and are made accessible to the user. XPIO supports both high-performance interfaces and low-speed SDR/DDR interfaces. Using XPHY, XPIO enables data stream alignment, serialization, and deserialization. Supported I/O standards include bank voltages of 1.0 V, 1.2 V, 1.35 V, and 1.5 V.

The SC-OBC Module V1 provides 54 XPIO signals to the user. To use the Versal PL XPIO, the bank power must be supplied from the carrier board via VCCO_703, and the user can select any of the bank voltages supported by the Versal device.

Versal GTY/GTYP 0/1

Versal GTY/GTYP are high-speed PIPE transceivers integrated into Versal devices. These GTY/GTYP transceivers can be connected to a PCIe controller or a High-Speed Debug Port (HSDP).

The SC-OBC Module V1 provides users with two GTY/GTYP interfaces, each featuring two pairs of clock signals, four pairs of transmit (TX) signals, and four pairs of receive (RX) signals.

IGLOO2 MSIO 0/1

IGLOO2 MSIO 0/1 are I/O signals connected to the MSIO of the IGLOO2 device and are made accessible to the user. IGLOO2’s MSIO (Multi-Standard I/O) is a highly flexible, general-purpose I/O that supports a wide range of I/O standards. Supported I/O standards are bank voltages of 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V. IGLOO2 MSIO 0 provides 32 MSIO lines, while IGLOO2 MSIO 1 provides 16 MSIO lines.

To use IGLOO2 MSIO 0/1, the bank power supply must be provided from the carrier board via M2GL_VDDI8 and M2GL_VDDI5. This allows the user to select any bank voltage supported by IGLOO2.

Power Input/Output

The SC-OBC Module V1 operates primarily on a single 5 V power supply provided by the carrier board. However, by supplying power to the IO banks from the carrier board, signals of any voltage level can be connected to the IO bank signals. For this purpose, the SC-OBC Module V1 includes dedicated pathways for the IO bank power input.

The SC-OBC Module V1 generates power internally from the 5 V input from the carrier board and outputs it as a power supply line. This output is intended as a power supply for circuits on the carrier board. Furthermore, depending on the carrier board design, this output power can also be connected to the module’s VCCO input pin to serve as the power supply for the module’s IO banks.

The power lines available via the SC-OBC Module V1’s board-to-board connector are as follows:

Table 19. Power Input/Output List
VIN_5V0 Power Input 5 Main power input from the carrier board

VCC_BATT_IN

Power Input

1.2 - 1.5

Power input for the real-time clock (RTC)

VDD_3V3_OUT

Power Output

3.3

3.3V power output for user circuit

VDD_1V8_OUT

Power Output

1.8

1.8V power output for user circuit

VDD_1V2_OUT

Power Output

1.2

1.2V power output for user circuit

VCCO_500_501_OUT

Power Output

1.8

Versal Bank 500 /501 1.8V power output

VCCO_503_OUT

Power Output

1.8

Versal Bank 503 (JTAG) 1.8V power output

M2GL_VDDI4_OUT

Power Output

1.8

IGLOO2 Bank 4 (JTAG) 1.8V power output

VCCO_502_IN

IO Bank Power Input

1.8/2.5/3.3

Power input for Versal LPD MIO Bank 502

VCCO_703_IN

IO Bank Power Input

1.0/1.2/1.35/1.5

Power input for Versal PL XPIO Bank 703

VCCO_302_IN

IO Bank Power Input

1.8/2.5/3.3

Power input for Versal PL HDIO Bank 302

M2GL_VDDI5_IN

IO Bank Power Input

1.2/1.5/1.8/2.5/3.3

Power input for IGLOO2 Bank 5

M2GL_VDDI8_IN

IO Bank Power Input

1.2/1.5/1.8/2.5/3.3

Power input for IGLOO2 Bank 8

When VIN_5V0 is applied, the output power generated by the SC-OBC Module V1’s DC-DC converter supplies VDD_3V3_OUT, VDD_1V8_OUT and VDD_1V2_OUT, making them immediately available. Users can utilize these power rails to supply circuits on the carrier board. Each output includes overcurrent protection, with VDD_3V3_OUT rated for up to 1 A and VDD_1V8_OUT and VDD_1V2_OUT rated for up to 300 mA.

Power Up Timing
Figure 2. Power Up Timing

The table above defines two types of Power Enable signals for the three IO bank power inputs, enabling arbitrary power-saving control. Both signals are output from the SC-OBC Module V1 and wired to the carrier board. When the _PWREN line is asserted, the carrier board should supply power to the corresponding power input pin. When deasserted, power supply may be stopped to reduce standby current and overall power consumption. Alternatively, a configuration in which power is supplied continuously regardless of the Power Enable signal’s state is also acceptable.

Specifically, the following applies:

  • VCCO_302_703_PWREN controls both VCCO_302_IN and VCCO_703_IN

  • VCCO_502_PWREN controls VCCO_502_IN

Power Control by PWREN Signals
Figure 3. Power Control by PWREN Signals
Table 20. Power Input/Output List
IO Bank Power Input Power Enable Signal

VCCO_502_IN

VCCO_502_PWREN

VCCO_302_IN

VCCO_302_703_PWREN

VCCO_703_IN

M2GL_VDDI5_IN

N/A

M2GL_VDDI8_IN

N/A

Example LPD MIO Connection Circuit on the Carrier Board

The following shows an example configuration on the carrier board side for connecting a device requiring a 1.8 V power supply to LPD MIO Bank 502.

Carrier Board Design Example with LPD MIO Bank 502
Figure 4. Carrier Board Design Example with LPD MIO Bank 502

When using the LPD MIO Bank 502, power must be supplied to pin VCCO_502_IN. Since VCCO_502_IN has a corresponding Power Enable signal, VCCO_502_PWREN, this signal can be used as the enable input to generate VCCO_502_IN. In this example, VDD_1V8_OUT is used as the power source to supply 1.8 V to devices on the carrier board. A power switch controlled by VCCO_502_PWREN controls the supply to VCCO_502_IN.

Example PMC MIO Connection Circuit on the Carrier Board

The following shows an example configuration on the carrier board for connecting a device requiring both 1.8 V and 3.3 V power supplies, such as an eMMC, to PMC MIO Bank 500.

Carrier Board Design Example with PMC MIO Bank 500
Figure 5. Carrier Board Design Example with PMC MIO Bank 500

Example PL HDIO Connection Circuit on Carrier Board

The following shows an example configuration on the carrier board side for connecting a device requiring a 3.3 V power supply to PL HDIO Bank 302.

Carrier Board Design Example with PL HDIO Bank 302
Figure 6. Carrier Board Design Example with PL HDIO Bank 302